/* TODO : * a couple of size 1 registers are not spec'ed correctly yet due to HAIL * compiler limit. */ device smc91c111 { register_map mac { .= default { stride = 2; size = 2; access = rw; write_value = dont_change; read_value = volatile; } .=0xe { name = BSR; /* used in IRQ */ access = rw; read_value = volatile; [ 15:8 ] : ID; write_value=dont_matter; read_value = fixed(0x33); [ 7:3 ] : reserved; read_value = dont_matter; [ 2:0 ] : BANK; } /* Bank 0 */ .=0 { name = TCR; /* used in IRQ */ access = rw; read_value=static; write_value=dont_change; [ 15 ] : SWFDUP; [ 14 ] : reserved; [ 13 ] : EPH_LOOP; [ 12 ] : STP_SQET; [ 11 ] : FDUPLX; [ 10 ] : MON_CSN; [ 9 ] : reserved; [ 8 ] : NOCRC; [ 7 ] : PAD_EN; [ 6 ] : reserved; [ 5 ] : reserved; [ 4 ] : reserved; [ 3 ] : reserved; [ 2 ] : FORCOL; [ 1 ] : LOOP; [ 0 ] : TXENA; read_value=volatile; } .=2 { name = EPHSR; access = ro; [ 15 ] : TX_UNRN; [ 14 ] : LINK_OK; [ 13 ] : reserved; [ 12 ] : CTR_ROL; [ 11 ] : EXC_DEF; [ 10 ] : LOST_CAR; [ 9 ] : LATCOL; [ 8 ] : reserved; [ 7 ] : TX_DEFR; [ 6 ] : LTX_BRD; [ 5 ] : SQET; [ 4 ] : COL16; [ 3 ] : LTX_MULT; [ 2 ] : MUL_COL; [ 1 ] : SNGL_COL; [ 0 ] : TX_SUC; } .=4 { name = RCR; access = rw; read_value=static; [ 15 ] : SOFT_RST; [ 14 ] : FILT_CAR; [ 13 ] : ABORT_ENB; [ 12 ] : reserved; [ 11 ] : reserved; [ 10 ] : reserved; [ 9 ] : STRIP_CRC; [ 8 ] : RXEN; [ 7 ] : reserved; [ 6 ] : reserved; [ 5 ] : reserved; [ 4 ] : reserved; [ 3 ] : reserved; [ 2 ] : ALMUL; [ 1 ] : PRMS; [ 0 ] : RX_ABORT; read_value=volatile; write_value=fixed(0); } .=6 { name = ECR; access = ro; [ 15:12 ] : EXDTX; [ 11:8 ] : DTX; [ 7:4 ] : MCOLN; [ 3:0 ] : COLN; } .=8 { name = MIR; access = ro; [ 15:8 ] : AVAIL; [ 7:0 ] : SIZE; read_value=static; } .=0xa { name = RPCR; access = rw; read_value=static; [ 15 ] : reserved; [ 14 ] : reserved; [ 13 ] : SPEED; [ 12 ] : DPLX; [ 11 ] : ANEG; [ 10 ] : reserved; [ 9 ] : reserved; [ 8 ] : reserved; [ 7:5 ] : LEDA; enum = { LINK10or100=0x0, LINK10=0x2, FDX=0x3, TXRX=0x4, LINK100=0x5, RX=0x6, TX=0x7 }; [ 4:2 ] : LEDB; enum = { LINK10or100=0x0, LINK10=0x2, FDX=0x3, TXRX=0x4, LINK100=0x5, RX=0x6, TX=0x7 }; [ 1 ] : reserved; [ 0 ] : reserved; } /* Bank 1 */ .=0 { name = CR; access = rw; read_value=static; [ 15 ] : EPH_Power_EN; [ 14 ] : reserved; [ 13 ] : reserved; [ 12 ] : NO_WAIT; [ 11 ] : reserved; [ 10 ] : GPCNTRL; [ 9 ] : EXT_PHY; [ 8 ] : reserved; [ 7 ] : reserved; [ 6 ] : reserved; [ 5:3 ] : reserved; [ 2 ] : reserved; [ 1 ] : reserved; [ 0 ] : reserved; } .=2 { name = BAR; access = rw; read_value=static; [ 15:13 ] : A15_13; [ 12:8 ] : A9_5; [ 7:1 ] : reserved; [ 0 ] : reserved; } .=4 { name = IAR1_0; access = rw; read_value=static; [ 15:8 ] : A1; [ 7:0 ] : A0; } .=6 { name = IAR3_2; access = rw; read_value=static; [ 15:8 ] : A3; [ 7:0 ] : A2; } .=8 { name = IAR5_4; access = rw; read_value=static; [ 15:8 ] : A5; [ 7:0 ] : A4; } .=0xa { name = GPR; access = rw; read_value=static; [ 15:0 ] : DATA; } .=0xc { name = CTR; access = rw; read_value=static; [ 15 ] : reserved; [ 14 ] : RCV_BAD; [ 13 ] : reserved; [ 12 ] : reserved; [ 11 ] : AUTO_RELEASE; [ 10 ] : reserved; [ 9 ] : reserved; [ 8 ] : reserved; [ 7 ] : LE_ENABLE; [ 6 ] : CR_ENABLE; [ 5 ] : TE_ENABLE; [ 4 ] : reserved; [ 3 ] : reserved; [ 2 ] : EEPROM_SELECT; [ 1 ] : RELOAD; read_value=volatile; [ 0 ] : STORE; read_value=volatile; } /* Bank 2 */ .=0 { name = MMUCR; /* used in IRQ */ access = rw; [ 15 ] : reserved; [ 14 ] : reserved; [ 13 ] : reserved; [ 12 ] : reserved; [ 11 ] : reserved; [ 10 ] : reserved; [ 9 ] : reserved; [ 8 ] : reserved; [ 7:5 ] : CMD; write_value=explicit; enum = { NOOP=0x0, TX_ALLOC=0x1, MMU_RESET=0x2, RX_FIFO_RM=0x3, RX_FIFO_RnR=0x4, RELEASE_PNO=0x5, ENQUEUE_PNO=0x6, RESET_TX_FIFOS=0x7 }; [ 4 ] : reserved; [ 3 ] : reserved; [ 2 ] : reserved; [ 1 ] : reserved; [ 0 ] : BUSY; write_value=fixed(0); } /* .=2 { name = PNR; access = rw; read_value=static; size = 1; [ 7 ] : reserved; [ 6 ] : reserved; [ 5:0 ] : PACKET_NUMBER_AT_TX_AREA; } .=3 { name = ARR; access = ro; size = 1; [ 7 ] : FAILED; [ 6 ] : reserved; [ 5:0 ] : ALLOCATED_PACKET_NUMBER; } */ .=2 { name = PNR; /* used in IRQ */ access = rw; read_value=static; [15:8] : reserved; [ 7 ] : reserved; [ 6 ] : reserved; [ 5:0 ] : PACKET_NUMBER_AT_TX_AREA; } .=2 { name = ARR; access = ro; [ 15 ] : FAILED; [ 14 ] : reserved; [ 13:8 ] : ALLOCATED_PACKET_NUMBER; [7:0 ] : reserved; } .=4 { name =FIFO; /* used in IRQ */ access = ro; read_value = volatile; [ 15 ] : REMPTY; [ 14 ] : reserved; [ 13:8 ] : RX_FIFO_PACKET_NUMBER; [ 7 ] : TEMPTY; [ 6 ] : reserved; [ 5:0 ] : TX_FIFO_PACKET_NUMBER; } .=6 { name = PTR; access = rw; /* used in IRQ */ write_value=explicit; [ 15 ] : RCV; read_value=static; [ 14 ] : AUTO_INCR; read_value=static; [ 13 ] : READ; read_value=static; [ 12 ] : ETEN; read_value=static; [ 11 ] : NOT_EMPTY; write_value=dont_matter; [ 10:8 ] : POINTER_HIGH; [ 7:0 ] : POINTER_LOW; } .=8 { name = DATA; /* used in IRQ */ access = rw; read_value=volatile_se; write_value=explicit; size = 2; [15:0] : DATA; } /* .=0xc { name = IST; access = ro; size = 1; [ 7 ] : MDINT; [ 6 ] : ERCV_INT; [ 5 ] : EPH_INT; [ 4 ] : RX_OVRN_INT; [ 3 ] : ALLOC_INT; [ 2 ] : TX_EMPTY_INT; [ 1 ] : TX_INT; [ 0 ] : RCV_INT; } .=0xc { name = ACK; access = wo; write_value=explicit; size = 1; [ 7 ] : MDINT; [ 6 ] : ERCV_INT; [ 5 ] : reserved; [ 4 ] : RX_OVRN_INT; [ 3 ] : reserved; [ 2 ] : TX_EMPTY_INT; [ 1 ] : TX_INT; [ 0 ] : reserved; } .=0xd { name = MSK; access = rw; read_value=static; size = 1; [ 7 ] : MDINT; [ 6 ] : ERCV_INT; [ 5 ] : EPH_INT; [ 4 ] : RX_OVRN_INT; [ 3 ] : ALLOC_INT; [ 2 ] : TX_EMPTY_INT; [ 1 ] : TX_INT; [ 0 ] : RCV_INT; } */ .=0xc { name = IST; access = ro; [15:8] : reserved; [ 7 ] : MDINT; [ 6 ] : ERCV_INT; [ 5 ] : EPH_INT; [ 4 ] : RX_OVRN_INT; [ 3 ] : ALLOC_INT; [ 2 ] : TX_EMPTY_INT; [ 1 ] : TX_INT; [ 0 ] : RCV_INT; } .=0xc { name = ACK; access = wo; write_value=explicit; [15:8] : reserved; [ 7 ] : MDINT; [ 6 ] : ERCV_INT; [ 5 ] : reserved; [ 4 ] : RX_OVRN_INT; [ 3 ] : reserved; [ 2 ] : TX_EMPTY_INT; [ 1 ] : TX_INT; [ 0 ] : reserved; } .=0xc { name = MSK; /* used in IRQ */ access = rw; read_value=static; [ 15 ] : MDINT; [ 14 ] : ERCV_INT; [ 13 ] : EPH_INT; [ 12 ] : RX_OVRN_INT; [ 11 ] : ALLOC_INT; [ 10 ] : TX_EMPTY_INT; [ 9 ] : TX_INT; [ 8 ] : RCV_INT; [7:0] : reserved; write_value=fixed(0); } /* Bank 3 */ .=0 { name = MT1_0; access = rw; read_value=static; [ 15:8 ] : MT1; [ 7:0 ] : MT0; } .=2 { name = MT3_2; access = rw; read_value=static; [ 15:8 ] : MT3; [ 7:0 ] : MT2; } .=4 { name = MT5_4; access = rw; read_value=static; [ 15:8 ] : MT5; [ 7:0 ] : MT4; } .=6 { name = MT7_6; access = rw; read_value=static; [ 15:8 ] : MT7; [ 7:0 ] : MT6; } .=8 { name = MGMT; /* used in IRQ */ access = rw; read_value=volatile; write_value=explicit; [ 15 ] : reserved; [ 14 ] : MSK_CRS100; [ 13 ] : reserved; [ 12 ] : reserved; [ 11 ] : reserved; [ 10 ] : reserved; [ 9 ] : reserved; [ 8 ] : reserved; [ 7:4 ] : reserved; [ 3 ] : MDOE; [ 2 ] : MCLK; [ 1 ] : MDIN; [ 0 ] : MDOUT; } .=0xa { name = REV; access = ro; read_value=static; [ 15:8 ] : reserved; read_value=fixed(0x33); [ 7:4 ] : CHIP; read_value=fixed(0x9); [ 3:0 ] : REV; read_value=fixed(0x1); } .=0xc { name = ERCV; access = rw; write_value=explicit; [ 15:8 ] : reserved; [ 7 ] : RCV_DISCRD; [ 6 ] : reserved; [ 5 ] : reserved; [ 4:0 ] : ERCV_THRESHOLD; } } register_map phy { .= default { size = 2; access = rw; write_value = explicit; read_value = volatile; } .=0x0 { name = Control; /* Basic Mode Control */ write_value=dont_change; read_value=static; [ 15 ] : RST; read_value = volatile; /* self-clearing */ [ 14 ] : LPBK; [ 13 ] : SPEED; [ 12 ] : ANEG_EN; [ 11 ] : PDN; [ 10 ] : MII_DIS; [ 9 ] : ANEG_RST; read_value = volatile; /* self-clearing */ [ 8 ] : DPLX; [ 7 ] : COLST; [ 6:0 ] : reserved; write_value = fixed(0); } .=0x1 { name = Status; /* Basic Mode Status */ access = ro; [ 15 ] : CAP_T4; [ 14 ] : CAP_TXF; [ 13 ] : CAP_TXH; [ 12 ] : CAP_TF; [ 11 ] : CAP_TH; [ 10:7 ] : reserved; write_value = fixed(0); [ 6 ] : CAP_SUPR; [ 5 ] : ANEG_ACK; [ 4 ] : REM_FLT; [ 3 ] : CAP_ANEG; [ 2 ] : LINK; read_value = volatile_se; /* latch lo */ [ 1 ] : JAB; read_value = volatile_se; /* latch hi */ [ 0 ] : EXREG; } .=0x2 { name = PHY_ID1; /* PHY Identifier 1 */ access = ro; [ 15:0 ] : VENDOR; } .=0x3 { name = PHY_ID2; /* PHY Identifier 2 */ access = ro; [ 15:10 ] : OUILSB; [ 9:4 ] : MFGR; [ 3:0 ] : REV; } .=0x4 { name = ANA; /* Auto-Negotiation Advertisement */ [ 15 ] : NP; [ 14 ] : ACK; access = ro; [ 13 ] : RF; [ 12:10 ] : reserved; [ 9 ] : T4; [ 8 ] : TX_FDX; [ 7 ] : TX_HDX; [ 6 ] : TEN_FDX; [ 5 ] : TEN_HDX; [ 4:1 ] : reserved; [ 0 ] : CSMA; } .=0x5 { name = ANREC; /* Auto-Negotiation Remote End Capability */ access = ro; [ 15 ] : NP; [ 14 ] : ACK; [ 13 ] : RF; [ 12:10 ] : reserved; [ 9 ] : T4; [ 8 ] : TX_FDX; [ 7 ] : TX_HDX; [ 6 ] : TEN_FDX; [ 5 ] : TEN_HDX; [ 4:1 ] : reserved; [ 0 ] : CSMA; } .=0x10 { name = Config1; /* Configuration 1 */ read_value=static; write_value=dont_change; [ 15 ] : LNKDIS; [ 14 ] : XMTDIS; [ 13 ] : XMTPDN; [ 12:11 ] : reserved; write_value = fixed(0); [ 10 ] : BYPSCR; [ 9 ] : UNSCDS; [ 8 ] : EQLZR; [ 7 ] : CABLE; [ 6 ] : RLVL; [ 5:2 ] : TLVL; [ 1:0 ] : TRF; } .=0x11 { name = Config2; /* Configuration 2 */ read_value=static; write_value=dont_change; [ 15:6 ] : reserved; access = ro; write_value = dont_change; [ 5 ] : APOLDIS; [ 4 ] : JABDIS; [ 3 ] : MREG; [ 2 ] : INTMDIO; [ 1:0 ] : reserved; write_value = dont_change; } .=0x12 { name = Status_Output; /* Status Output */ access = ro; [ 15 ] : INT; [ 14 ] : LNKFAIL; read_value = volatile_se; /* ro, latch-on-transition */ [ 13 ] : LOSSSYNC; read_value = volatile_se; /* ro, latch-on-transition */ [ 12 ] : CWRD; read_value = volatile_se; /* ro, latch-on-transition */ [ 11 ] : SSD; read_value = volatile_se; /* ro, latch-on-transition */ [ 10 ] : ESD; read_value = volatile_se; /* ro, latch-on-transition */ [ 9 ] : RPOL; read_value = volatile_se; /* ro, latch-on-transition */ [ 8 ] : JAB; read_value = volatile_se; /* ro, latch-on-transition */ [ 7 ] : SPDDET; read_value = volatile_se; /* ro, latch-on-transition */ [ 6 ] : DPLXDET; read_value = volatile_se; /* ro, latch-on-transition */ [ 5:0 ] : reserved; } .=0x13 { name = Mask; /* Mask */ read_value=static; write_value=dont_change; [ 15 ] : MINT; [ 14 ] : MLNKFAIL; [ 13 ] : MLOSSSYN; [ 12 ] : MCWRD; [ 11 ] : MSSD; [ 10 ] : MESD; [ 9 ] : MRPOL; [ 8 ] : MJAB; [ 7 ] : MSPDDT; [ 6 ] : MDPLDT; [ 5:0 ] : reserved; } .=0x14 { name = Reserved; /* Reserved */ [ 15:0 ] : reserved; } } } invariant { ( r(BSR_BANK) == 0) { rw(TCR) } ; ( r(BSR_BANK) == 0) { rw(EPHSR) } ; ( r(BSR_BANK) == 0) { rw(RCR) } ; ( r(BSR_BANK) == 0) { rw(ECR) } ; ( r(BSR_BANK) == 0) { rw(MIR) } ; ( r(BSR_BANK) == 0) { rw(RPCR) } ; ( r(BSR_BANK) == 1) { rw(BAR) } ; ( r(BSR_BANK) == 1) { rw(IAR0_1) } ; ( r(BSR_BANK) == 1) { rw(IAR2_3) } ; ( r(BSR_BANK) == 1) { rw(IAR4_5) } ; ( r(BSR_BANK) == 1) { rw(GPR) } ; ( r(BSR_BANK) == 1) { rw(CTR) } ; ( r(BSR_BANK) == 1) { rw(CR) } ; ( r(BSR_BANK) == 2) { rw(MMUCR) } ; ( r(BSR_BANK) == 2) { rw(PNR) } ; ( r(BSR_BANK) == 2) { rw(ARR) } ; ( r(BSR_BANK) == 2) { rw(DATA) } ; ( r(BSR_BANK) == 2) { rw(IST) } ; ( r(BSR_BANK) == 2) { rw(ACK) } ; ( r(BSR_BANK) == 2) { rw(MSK) } ; ( r(BSR_BANK) == 2) { rw(FIFO) } ; ( r(BSR_BANK) == 3) { rw(MT1_0) } ; ( r(BSR_BANK) == 3) { rw(MT3_2) } ; ( r(BSR_BANK) == 3) { rw(MT5_4) } ; ( r(BSR_BANK) == 3) { rw(MT7_6) } ; ( r(BSR_BANK) == 3) { rw(MGMT) } ; ( r(BSR_BANK) == 3) { rw(REV) } ; ( r(BSR_BANK) == 3) { rw(ERCV) } ; /* 16COL, SQET, LOST_CARR and LATCOL can only happen in half duplex */ { r(EPHSR) } ( (m(EPHSR_COL16) == 0 && m(EPHSR_SQET) == 0 && m(EPHSR_LOST_CAR) == 0 && m(EPHSR_LATCOL) == 0) || (r(TCR_SWFDUP) == 0) ); /* EXT PHY must be 0 in order to access internal phy */ ( r(BSR_BANK) != 1 || r(CR_EXT_PHY) == 0 ) { rw(Status), rw(Control) }; /* Release command should not be issued when when the previous one is still in process */ ( ((r(MMUCR_CMD) != 4) && r(MMUCR_CMD) != 5) || r(MMUCR_BUSY) == 0) { w(MMUCR) }; }; gated_spec smc91c111_mii { data_width = { 2 }; access_function = smc91c111_mii; /* smc91c111_mii_get_2(a) */ /* smc91c111_mii_set_2(a, v) */ }; instantiate my_smc91c111 as smc91c111 { multi_instance = no; mac => cpu_virtual { base_address = literal(smc91_base); }; phy => smc91c111_mii { base_address = static(0); }; }