diff -Nru src/sys/dev/ic/smc91cxxvar.h.orig src/sys/dev/ic/smc91cxxvar.h --- src/sys/dev/ic/smc91cxxvar.h.orig 2005-09-13 15:15:49.000000000 -0700 +++ src/sys/dev/ic/smc91cxxvar.h 2005-09-13 15:17:30.000000000 -0700 @@ -64,6 +64,7 @@ #define SMC_FLAGS_HAS_MII 0x0004 /* Has MII (FEAST) */ #define SMC_FLAGS_32BIT_READ 0x0008 /* reads are always 32-bits */ #define SMC_FLAGS_32BIT_DATA 0x0010 /* */ +#define SMC_FLAGS_NO_WAIT_ST 0x0020 /* disable wait state */ u_int8_t sc_chipid; u_int8_t sc_internal_phy; /* 91C111 only */ diff -Nru src/sys/dev/ic/smc91cxx.c.orig src/sys/dev/ic/smc91cxx.c --- src/sys/dev/ic/smc91cxx.c.orig 2005-09-13 14:55:11.000000000 -0700 +++ src/sys/dev/ic/smc91cxx.c 2005-09-13 15:32:22.000000000 -0700 @@ -139,7 +139,11 @@ #include #include -#include +/* static */ char *smc91_base; +extern u_int16_t smc91c111_mii_get_2(unsigned long); +extern void smc91c111_mii_set_2(unsigned long, u_int16_t); +#include + #include #ifndef __BUS_SPACE_HAS_STREAM_METHODS @@ -181,6 +185,27 @@ }; #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) +#define CHIP_91100 7 /* TMP -- use HAIL enum for CHIP_REV values */ +#define CHIP_91100FD 8 /* TMP -- use HAIL enum for CHIP_REV values */ +#define CHIP_91C111 9 /* TMP -- use HAIL enum for CHIP_REV values */ + +#define MIR_MULT_91C111 1 /* TMP -- use HAIL enum for MIR_SIZE values */ +#define MIR_SCALE_91C9x 256 /* TMP -- use HAIL enum for MIR_SCALE values */ +#define MIR_SCALE_91C111 2048 /* TMP -- use HAIL enum for MIR_SCALE values */ + +#define MEMORY_WAIT_TIME 1000 + +/* bits from smc91cxx RX header (in front of receive packet) */ +#define RS_MULTICAST 0x0001 /* Packet is multicast */ +#define RS_HASH_MASK 0x007e /* Mask of multicast hash value */ +#define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */ +#define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */ +#define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */ +#define RS_BADCRC 0x2000 /* Frame had CRC error */ +#define RS_ALGNERR 0x8000 /* Frame had alignment error */ +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) +#define RLEN_MASK 0x07ff /* Significant length bits in RX length */ + /* * MII bit-bang glue. */ @@ -191,11 +216,11 @@ smc91cxx_mii_bitbang_read, smc91cxx_mii_bitbang_write, { - MR_MDO, /* MII_BIT_MDO */ - MR_MDI, /* MII_BIT_MDI */ - MR_MCLK, /* MII_BIT_MDC */ - MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ - 0, /* MII_BIT_DIR_PHY_HOST */ + HAIL_MGMT_MDOUT_VAL(1), /* MII_BIT_MDO */ + HAIL_MGMT_MDIN_VAL(1), /* MII_BIT_MDI */ + HAIL_MGMT_MCLK_VAL(1), /* MII_BIT_MDC */ + HAIL_MGMT_MDOE_VAL(1), /* MII_BIT_DIR_HOST_PHY */ + 0, /* MII_BIT_DIR_PHY_HOST */ } }; @@ -220,6 +245,49 @@ void smc91cxx_watchdog __P((struct ifnet *)); int smc91cxx_ioctl __P((struct ifnet *, u_long, caddr_t)); +#undef SMC_SELECT_BANK +#define SMC_SELECT_BANK(s, b) set_BSR_BANK(b) +static inline void set_smc91_base __P((bus_space_tag_t, bus_space_handle_t)); +static inline void +set_smc91_base(bus_space_tag_t bst, bus_space_handle_t bsh) +{ + smc91_base = (char *)bsh; /* XXX */ +} + +static inline void set_DATA_multi_stream_2(u_int16_t *, unsigned int); +static inline void +set_DATA_multi_stream_2(u_int16_t *p, unsigned int len) +{ + u_int16_t *ioa = (u_int16_t *)(smc91_base + 8); + while (len--) + *ioa = *p++;; +} + +static inline void mem_get_DATA_multi_stream_2(u_int16_t *, unsigned int); +static inline void +mem_get_DATA_multi_stream_2(u_int16_t *p, unsigned int len) +{ + u_int16_t *ioa = (u_int16_t *)(smc91_base + 8); + while(len--) + *p++ = *ioa; +} + +static inline u_int8_t get_DATA_B(void); +static inline u_int8_t +get_DATA_B() +{ + volatile u_int8_t *p = (volatile u_int8_t *)(smc91_base + 8); + return *p; + +} + +static inline void +set_DATA_B(u_int8_t v) +{ + volatile u_int8_t *p = (volatile u_int8_t *)(smc91_base + 8); + *p = v; +} + static __inline int ether_cmp __P((void *, void *)); static __inline int ether_cmp(va, vb) @@ -248,10 +316,10 @@ int i, aui, mult, scale, memsize; char pbuf[9]; - tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); - /* check magic number */ - if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { - aprint_error("%s: failed to detect chip, bsr=%04x\n", + set_smc91_base(bst, bsh); + tmp = get_BSR_ID(); + if (tmp != 0x33) { + aprint_error("%s: failed to detect chip, BSR_ID=%04x\n", sc->sc_dev.dv_xname, tmp); return; } @@ -260,8 +328,8 @@ smc91cxx_stop(sc); SMC_SELECT_BANK(sc, 3); - tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); - sc->sc_chipid = RR_ID(tmp); + tmp = get_REV(); + sc->sc_chipid = mem_get_REV_CHIP(tmp); idstr = smc91cxx_idstrs[sc->sc_chipid]; aprint_normal("%s: ", sc->sc_dev.dv_xname); @@ -269,20 +337,19 @@ aprint_normal("%s, ", idstr); else aprint_normal("unknown chip id %d, ", sc->sc_chipid); - aprint_normal("revision %d, ", RR_REV(tmp)); + aprint_normal("revision %d, ", mem_get_REV_REV(tmp)); SMC_SELECT_BANK(sc, 0); switch (sc->sc_chipid) { default: - mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); - scale = MIR_SCALE_91C9x; - break; + panic("%s: unsupported chip id %#x\n", + sc->sc_dev.dv_xname, sc->sc_chipid); case CHIP_91C111: mult = MIR_MULT_91C111; scale = MIR_SCALE_91C111; } - memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; + memsize = get_MIR_SIZE(); if (memsize == 255) memsize++; memsize *= scale * mult; @@ -293,11 +360,18 @@ SMC_SELECT_BANK(sc, 1); if (myea == NULL) { myea = enaddr; - for (i = 0; i < ETHER_ADDR_LEN; i += 2) { - tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); - myea[i + 1] = (tmp >> 8) & 0xff; - myea[i] = tmp & 0xff; - } + /* + * XXX no indexed addressing methods in HAIL API + */ + tmp = get_IAR1_0(); + myea[0 + 1] = (tmp >> 8) & 0xff; + myea[0] = tmp & 0xff; + tmp = get_IAR3_2(); + myea[2 + 1] = (tmp >> 8) & 0xff; + myea[2] = tmp & 0xff; + tmp = get_IAR5_4(); + myea[4 + 1] = (tmp >> 8) & 0xff; + myea[4] = tmp & 0xff; } aprint_normal("%s: MAC address %s, ", sc->sc_dev.dv_xname, ether_sprintf(myea)); @@ -327,7 +401,7 @@ ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); SMC_SELECT_BANK(sc, 1); - tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); + tmp = get_CR(); miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; switch (sc->sc_chipid) { @@ -339,12 +413,24 @@ miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); case CHIP_91100FD: case CHIP_91C111: - if (tmp & CR_MII_SELECT) { + if (mem_get_CR_EPH_Power_EN(tmp)) { aprint_normal("default media MII"); if (sc->sc_chipid == CHIP_91C111) { - aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? - "external" : "internal"); - sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); + /* + * XXX CR_AUI_SELECT bit (0x0100) is reserved on 91c111 + * XXX using EXT_PHY bit (0x0200) instead for external/internal + */ + u_int8_t in; + char *str; + if (mem_get_CR_EXT_PHY(tmp)) { + str = "external"; + in = 0; + } else { + str = "internal"; + in = 1; + } + aprint_normal(" (%s PHY)\n", str); + sc->sc_internal_phy = in; } else aprint_normal("\n"); mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, @@ -371,7 +457,11 @@ } /*FALLTHROUGH*/ default: - aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? + /* + * XXX CR_AUI_SELECT bit (0x0100) is reserved on 91c111 + * XXX force UTP instead of relying on reserved bit + */ + aprint_normal("default media %s\n", (aui = (0)) ? "AUI" : "UTP"); for (i = 0; i < NSMC91CxxMEDIA; i++) ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); @@ -405,10 +495,6 @@ struct smc91cxx_softc *sc; int media; { - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; - u_int16_t tmp; - /* * If the interface is not currently powered on, just return. * When it is enabled later, smc91cxx_init() will properly set @@ -425,15 +511,6 @@ switch (IFM_SUBTYPE(media)) { case IFM_10_T: - case IFM_10_5: - SMC_SELECT_BANK(sc, 1); - tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); - if (IFM_SUBTYPE(media) == IFM_10_5) - tmp |= CR_AUI_SELECT; - else - tmp &= ~CR_AUI_SELECT; - bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); - delay(20000); /* XXX is this needed? */ break; default: @@ -452,9 +529,6 @@ struct ifmediareq *ifmr; { struct smc91cxx_softc *sc = ifp->if_softc; - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; - u_int16_t tmp; if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { ifmr->ifm_active = IFM_ETHER | IFM_NONE; @@ -473,9 +547,12 @@ } SMC_SELECT_BANK(sc, 1); - tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); - ifmr->ifm_active = - IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); + /* + * XXX CR_AUI_SELECT bit (0x0100) is reserved on 91c111 + * XXX avoid manipulating reserved bit + * XXX treat AUI as not possible + */ + ifmr->ifm_active = IFM_ETHER | IFM_10_T; } /* @@ -490,7 +567,7 @@ bus_space_handle_t bsh = sc->sc_bsh; u_int16_t tmp; u_int8_t *enaddr; - int s, i; + int s; s = splnet(); @@ -501,40 +578,43 @@ * * XXX how long are we really supposed to delay? --thorpej */ + set_smc91_base(bst, bsh); + if ((sc->sc_flags & SMC_FLAGS_NO_WAIT_ST) != 0) { + SMC_SELECT_BANK(sc, 1); + set_CR_NO_WAIT(1); + } SMC_SELECT_BANK(sc, 0); - bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); + set_RCR_SOFT_RST(1); delay(100); - bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); + set_RCR(0); delay(200); - - bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); + set_TCR(0); /* Set the Ethernet address. */ SMC_SELECT_BANK(sc, 1); enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); - for (i = 0; i < ETHER_ADDR_LEN; i += 2) { - tmp = enaddr[i + 1] << 8 | enaddr[i]; - bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); - } + set_IAR1_0( enaddr[0 + 1] << 8 | enaddr[0] ); + set_IAR3_2( enaddr[2 + 1] << 8 | enaddr[2] ); + set_IAR5_4( enaddr[4 + 1] << 8 | enaddr[4] ); /* * Set the control register to automatically release successfully * transmitted packets (making the best use of our limited memory) * and enable the EPH interrupt on certain TX errors. */ - bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | - CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); + tmp = HAIL_CTR_LE_ENABLE_VAL(1) | HAIL_CTR_CR_ENABLE_VAL(1) | HAIL_CTR_TE_ENABLE_VAL(1) | HAIL_CTR_AUTO_RELEASE_VAL(1); + set_CTR(tmp); /* * Reset the MMU and wait for it to be un-busy. */ SMC_SELECT_BANK(sc, 2); - bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); + set_MMUCR_CMD(MMUCR_MMU_RESET); for (;;) { - tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); + tmp = get_MMUCR(); if (tmp == 0xffff) /* card went away! */ return; - if ((tmp & MMUCR_BUSY) == 0) + if ((mem_get_MMUCR_BUSY(tmp)) == 0) break; } @@ -543,7 +623,7 @@ * Writes to both the acknowledge register and the mask register; * writing zero to the acknowledge register is a no-op. */ - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, 0); + set_MSK(0); /* * On the 91c111, enable auto-negotiation, and set the LED @@ -552,10 +632,7 @@ */ SMC_SELECT_BANK(sc, 0); if (sc->sc_chipid == CHIP_91C111) { - bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, - RPC_ANEG | - (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | - (RPC_LS_TXRX << RPC_LSB_SHIFT)); + set_RPCR(HAIL_RPCR_ANEG_VAL(1) | HAIL_RPCR_LEDA_VAL(RPCR_LINK10or100) | HAIL_RPCR_LEDB_VAL(RPCR_TXRX)); } /* @@ -572,42 +649,24 @@ * XXX all multicast. */ SMC_SELECT_BANK(sc, 0); - - tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; + tmp = HAIL_RCR_ALMUL_VAL(1) | HAIL_RCR_STRIP_CRC_VAL(1) | HAIL_RCR_RXEN_VAL(1); if (ifp->if_flags & IFF_PROMISC) - tmp |= RCR_PROMISC; + mem_set_RCR_PRMS(&tmp, 1); + set_RCR(tmp); - bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); - - /* - * Set transmitter control to "enabled". - */ - tmp = TCR_ENABLE; - -#ifndef SMC91CXX_SW_PAD - /* - * Enable hardware padding of transmitted packets. - * XXX doesn't work? - */ - tmp |= TCR_PAD_ENABLE; -#endif - - bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); +# ifndef SMC91CXX_SW_PAD + set_TCR_PAD_EN(1); +# endif + set_TCR_TXENA(1); /* * Now, enable interrupts. */ SMC_SELECT_BANK(sc, 2); - - if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, - (IM_EPH_INT | IM_RX_OVRN_INT | - IM_RCV_INT | IM_TX_INT | IM_MD_INT) << 8); - } else { - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, - (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT) - << 8); - } + tmp = HAIL_IST_TX_INT_VAL(1) | HAIL_IST_RCV_INT_VAL(1) | HAIL_IST_RX_OVRN_INT_VAL(1) | HAIL_IST_EPH_INT_VAL(1); + if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) + mem_set_IST_MDINT(&tmp, 1);; + set_MSK(tmp << 8); /* Interface is now running, with no output active. */ ifp->if_flags |= IFF_RUNNING; @@ -635,11 +694,10 @@ struct ifnet *ifp; { struct smc91cxx_softc *sc = ifp->if_softc; - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; u_int len; struct mbuf *m; - u_int16_t length, npages, isr; + u_int16_t length, npages; + u_int16_t isr; u_int8_t packetno; int timo, pad; @@ -695,19 +753,24 @@ /* * Now allocate the memory. */ - SMC_SELECT_BANK(sc, 2); - bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); + SMC_SELECT_BANK(sc, 2); + /* + * On the 91c111, it seems the bitfield used for `npages' + * is reserved -- i.e. `npages' need not be specified? + */ + set_MMUCR(npages | HAIL_MMUCR_CMD_VAL(MMUCR_TX_ALLOC)); timo = MEMORY_WAIT_TIME; do { - if (bus_space_read_2(bst, bsh, INTR_STAT_REG_W) & IM_ALLOC_INT) + if (get_IST_ALLOC_INT() != 0) break; delay(1); } while (--timo); - packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); + packetno = get_ARR() >> 8; - if (packetno & ARR_FAILED || timo == 0) { + if ((packetno & (HAIL_ARR_FAILED_VAL(1) >> 8)) || (timo == 0)) + { /* * No transmit memory is available. Record the number * of requestd pages and enable the allocation completion @@ -716,9 +779,10 @@ * no one else attempts to transmit while we're allocating * memory. */ - isr = bus_space_read_2(bst, bsh, INTR_STAT_REG_W) >> 8; - isr |= IM_ALLOC_INT; - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, isr << 8); + isr = get_MSK(); + isr >>= 8; + isr |= HAIL_IST_ALLOC_INT_VAL(1); + set_MSK(isr << 8); ifp->if_timer = 5; ifp->if_flags |= IFF_OACTIVE; @@ -729,19 +793,19 @@ /* * We have a packet number - set the data window. */ - bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); + set_PNR_PACKET_NUMBER_AT_TX_AREA(packetno); /* * Point to the beginning of the packet. */ - bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); + set_PTR(HAIL_PTR_AUTO_INCR_VAL(1)); /* * Send the packet length (+6 for stats, length, and control bytes) * and the status word (set to zeros). */ - bus_space_write_2(bst, bsh, DATA_REG_W, 0); - bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); + set_DATA(0); + set_DATA((length + 6) & 0x7ff); /* * Get the packet from the kernel. This will include the Ethernet @@ -759,29 +823,33 @@ * Push out padding. */ while (pad > 1) { - bus_space_write_2(bst, bsh, DATA_REG_W, 0); + set_DATA(0); pad -= 2; } if (pad) - bus_space_write_1(bst, bsh, DATA_REG_B, 0); -#endif + /* + * XXX TMP FIXME non-hail inline cheat 1 byte write + */ + set_DATA_B(0); +#endif /* SMC91CXX_SW_PAD */ /* * Push out control byte and unused packet byte. The control byte * is 0, meaning the packet is even lengthed and no special * CRC handling is necessary. */ - bus_space_write_2(bst, bsh, DATA_REG_W, 0); + set_DATA(0); /* * Enable transmit interrupts and let the chip go. Set a watchdog * in case we miss the interrupt. */ - isr = bus_space_read_2(bst, bsh, INTR_STAT_REG_W) >> 8; - isr |= IM_TX_INT | IM_TX_EMPTY_INT; - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, isr << 8); + isr = get_IST(); + isr >>= 8; + isr |= (HAIL_ACK_TX_INT_VAL(1) | HAIL_ACK_TX_EMPTY_INT_VAL(1)); + set_MSK(isr << 8); - bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); + set_MMUCR_CMD(MMUCR_ENQUEUE_PNO); ifp->if_timer = 5; @@ -800,7 +868,7 @@ * RX FIFO. If nothing has arrived, attempt to queue another * transmit packet. */ - if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) + if (get_FIFO_REMPTY() != 0) goto again; else smc91cxx_read(sc); @@ -814,8 +882,6 @@ struct smc91cxx_softc *sc; struct mbuf *m0; { - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; struct mbuf *m; int len, leftover; u_int16_t dbuf; @@ -848,7 +914,7 @@ */ dbuf |= *p++ << 8; len--; - bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); + set_DATA(dbuf); leftover = 0; } else if ((long) p & 1) { /* @@ -869,8 +935,8 @@ */ leftover = len & 1; len &= ~1; - bus_space_write_multi_stream_2(bst, bsh, - DATA_REG_W, (u_int16_t *)p, len >> 1); + set_DATA_multi_stream_2( + (u_int16_t *)p, len >> 1); p += len; if (leftover) @@ -880,6 +946,10 @@ /* 32-bit aligned data */ leftover = len & 3; len &= ~3; + /* + * XXX TMP FIXME cheat 4 byte write + * XXX to special (viper specific!) address + */ bus_space_write_multi_stream_4(sc->sc_d32t, sc->sc_d32h, 0, (u_int32_t *)p, len >> 2); p += len; @@ -895,7 +965,10 @@ #endif } if (leftover) - bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); + /* + * XXX TMP FIXME non-hail inline cheat 1 byte PIO write + */ + set_DATA_B(dbuf); } /* @@ -907,8 +980,6 @@ { struct smc91cxx_softc *sc = arg; struct ifnet *ifp = &sc->sc_ec.ec_if; - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; u_int8_t mask, interrupts, status; u_int16_t packetno, tx_status, card_stats, isr; @@ -921,14 +992,14 @@ /* * Obtain the current interrupt mask and interrupts which occurred. */ - isr = bus_space_read_2(bst, bsh, INTR_STAT_REG_W); + isr = get_IST(); mask = isr >> 8; + interrupts = isr & 0xff; /* * Get the set of interrupt which occurred and eliminate any * which are not enabled. */ - interrupts = isr & 0xff; status = interrupts & mask; /* Ours? */ @@ -938,49 +1009,38 @@ /* * It's ours; disable all interrupts while we process them. */ - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, 0); + set_MSK(0); /* * Receive overrun interrupts. */ - if (status & IM_RX_OVRN_INT) { - isr = bus_space_read_2(bst, bsh, INTR_STAT_REG_W); - isr = (isr & 0xff00) | IM_RX_OVRN_INT; - /* Acknowledge */ - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, isr); + if (status & HAIL_IST_RX_OVRN_INT_VAL(1)) { + isr = get_IST(); /* set_ACK_RX_OVRN_INT(1) */ + isr = (isr & 0xff00) | HAIL_IST_RX_OVRN_INT_VAL(1); + set_ACK(isr); ifp->if_ierrors++; } /* * Receive interrupts. */ - if (status & IM_RCV_INT) { -#if 1 /* DIAGNOSTIC */ - packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); - if (packetno & FIFO_REMPTY) { + if (status & HAIL_IST_RCV_INT_VAL(1)) { + if (get_FIFO_REMPTY()) { printf("%s: receive interrupt on empty fifo\n", sc->sc_dev.dv_xname); goto out; - } else -#endif + } smc91cxx_read(sc); } /* * Memory allocation interrupts. */ - if (status & IM_ALLOC_INT) { - /* Disable this interrupt. */ - mask &= ~IM_ALLOC_INT; - - /* - * Release the just-allocated memory. We will reallocate - * it through the normal start logic. - */ - while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) - /* XXX bound this loop! */ ; - bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); - + if (status & HAIL_IST_ALLOC_INT_VAL(1)) { + mask &= ~HAIL_IST_ALLOC_INT_VAL(1); + while (get_MMUCR_BUSY() != 0) + ; + set_MMUCR_CMD(MMUCR_RELEASE_PNO); ifp->if_flags &= ~IFF_OACTIVE; ifp->if_timer = 0; } @@ -990,61 +1050,63 @@ * This will only be called on error condition because of AUTO RELEASE * mode. */ - if (status & IM_TX_INT) { - isr = bus_space_read_2(bst, bsh, INTR_STAT_REG_W); - isr = (isr & 0xff00) | IM_TX_INT; + if (status & HAIL_IST_TX_INT_VAL(1)) + { + isr = get_IST(); + isr = (isr & 0xff00) | HAIL_IST_TX_INT_VAL(1); /* Acknowledge */ - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, isr); + set_ACK(isr); - packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & - FIFO_TX_MASK; + packetno = get_FIFO_TX_FIFO_PACKET_NUMBER(); /* * Select this as the packet to read from. */ - bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); + set_PNR(packetno); /* XXX + * set_PNR_PACKET_NUMBER_AT_TX_AREA() + * does rd-mod-wr, but ARR alias + * is access ro, so writing back + * e.g. ALLOCATED_PACKET_NUMBER + * may be incorrect + */ /* * Position the pointer to the beginning of the packet. */ - bus_space_write_2(bst, bsh, POINTER_REG_W, - PTR_AUTOINC | PTR_READ /* | 0x0000 */); + set_PTR(HAIL_PTR_AUTO_INCR_VAL(1) | HAIL_PTR_READ_VAL(1)); /* * Fetch the TX status word. This will be a copy of * the EPH_STATUS_REG_W at the time of the transmission * failure. */ - tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); - - if (tx_status & EPHSR_TX_SUC) + tx_status = get_DATA(); + if (mem_get_EPHSR_TX_SUC(tx_status)) printf("%s: successful packet caused TX interrupt?!\n", sc->sc_dev.dv_xname); else ifp->if_oerrors++; - if (tx_status & EPHSR_LATCOL) + if (mem_get_EPHSR_LATCOL(tx_status)) ifp->if_collisions++; /* * Some of these errors disable the transmitter; reenable it. */ SMC_SELECT_BANK(sc, 0); -#ifdef SMC91CXX_SW_PAD - bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); -#else - bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, - TCR_ENABLE | TCR_PAD_ENABLE); -#endif +# ifndef SMC91CXX_SW_PAD + set_TCR(HAIL_TCR_TXENA_VAL(1)); +# else + set_TCR(HAIL_TCR_TXENA_VAL(1) | HAIL_TCR_PAD_EN_VAL(1)); +# endif /* * Kill the failed packet and wait for the MMU to unbusy. */ SMC_SELECT_BANK(sc, 2); - while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) - /* XXX bound this loop! */ ; - bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); - + while (get_MMUCR_BUSY() != 0) + ; + set_MMUCR_CMD(MMUCR_RELEASE_PNO); ifp->if_timer = 0; } @@ -1052,31 +1114,32 @@ * Transmit underrun interrupts. We use this opportunity to * update transmit statistics from the card. */ - if (status & IM_TX_EMPTY_INT) { - isr = bus_space_read_2(bst, bsh, INTR_STAT_REG_W); - isr = (isr & 0xff00) | IM_TX_EMPTY_INT; - /* Acknowledge */ - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, isr); + if (status & HAIL_IST_TX_EMPTY_INT_VAL(1)) + { + /* + * the register model and/or hail APIs for IST, MSK and ACK + * are insufficient here + * need ability to operate on 16 or 8 bit sizes in variable + * ("memory") in order to manage operating 16 bit only + * bus constrained effective register size. + */ + isr = get_IST(); + isr = (isr & 0xff00) | HAIL_IST_TX_EMPTY_INT_VAL(1); + set_ACK(isr); /* Disable this interrupt. */ - mask &= ~IM_TX_EMPTY_INT; + mask &= ~HAIL_IST_TX_EMPTY_INT_VAL(1); SMC_SELECT_BANK(sc, 0); - card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); - - /* Single collisions. */ - ifp->if_collisions += card_stats & ECR_COLN_MASK; - - /* Multiple collisions. */ - ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; - + card_stats = get_ECR(); + ifp->if_collisions += mem_get_ECR_COLN(card_stats); + ifp->if_collisions += mem_get_ECR_MCOLN(card_stats); SMC_SELECT_BANK(sc, 2); - ifp->if_timer = 0; } if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && - (status & IM_MD_INT)) { + (status & HAIL_ACK_MDINT_VAL(1))) { /* * Internal PHY status change */ @@ -1086,7 +1149,7 @@ /* * Other errors. Reset the interface. */ - if (status & IM_EPH_INT) { + if (status & HAIL_MSK_EPH_INT_VAL(1)) { smc91cxx_stop(sc); smc91cxx_init(sc); } @@ -1101,14 +1164,13 @@ * Reenable the interrupts we wish to receive now that processing * is complete. */ - mask |= bus_space_read_2(bst, bsh, INTR_STAT_REG_W) >> 8; - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, mask << 8); + mask |= (get_MSK() >> 8); + set_MSK(mask << 8); #if NRND > 0 if (status) rnd_add_uint32(&sc->rnd_source, status); #endif - return (1); } @@ -1121,13 +1183,10 @@ struct smc91cxx_softc *sc; { struct ifnet *ifp = &sc->sc_ec.ec_if; - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; struct ether_header *eh; struct mbuf *m; - u_int16_t status, packetno, packetlen; + u_int16_t status, packetlen; u_int8_t *data; - u_int32_t dr; again: /* @@ -1135,24 +1194,16 @@ * PTR_RCV is set, the packet number will be found automatically * in FIFO_PORTS_REG_W, FIFO_RX_MASK. */ - bus_space_write_2(bst, bsh, POINTER_REG_W, - PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); + set_PTR(HAIL_PTR_AUTO_INCR_VAL(1) | HAIL_PTR_READ_VAL(1) | HAIL_PTR_RCV_VAL(1)); /* * First two words are status and packet length. */ if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { - status = bus_space_read_2(bst, bsh, DATA_REG_W); - packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); + status = get_DATA(); + packetlen = get_DATA(); } else { - dr = bus_space_read_4(bst, bsh, DATA_REG_W); -#if BYTE_ORDER == LITTLE_ENDIAN - status = (u_int16_t)dr; - packetlen = (u_int16_t)(dr >> 16); -#else - packetlen = (u_int16_t)dr; - status = (u_int16_t)(dr >> 16); -#endif + panic("%s:%d: SMC_FLAGS_32BIT_READ", __FUNCTION__, __LINE__); } packetlen &= RLEN_MASK; @@ -1210,23 +1261,26 @@ eh = mtod(m, struct ether_header *); data = mtod(m, u_int8_t *); - *(u_int16_t *)data = bus_space_read_2(bst, bsh, DATA_REG_W); + *(u_int16_t *)data = get_DATA(); data += 2; len -= 2; /* Now 4-byte aligned */ if (len > 3) { + /* + * XXX TMP FIXME cheat 4 byte write + * XXX to special (viper specific!) address + */ bus_space_read_multi_stream_4(sc->sc_d32t, sc->sc_d32h, 0, (u_int32_t *)data, len >> 2); data += len & ~3; } if (len & 2) { - *(u_int16_t *)data = - bus_space_read_2(bst, bsh, DATA_REG_W); + *(u_int16_t *)data = get_DATA(); data += 2; } if (len & 1) { - *data = bus_space_read_1(bst, bsh, DATA_REG_B); + *data = get_DATA_B(); } } else if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t) + @@ -1235,24 +1289,17 @@ eh = mtod(m, struct ether_header *); data = mtod(m, u_int8_t *); if (packetlen > 1) - bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, + mem_get_DATA_multi_stream_2( (u_int16_t *)data, packetlen >> 1); if (packetlen & 1) { data += packetlen & ~1; - *data = bus_space_read_1(bst, bsh, DATA_REG_B); + /* + * XXX TMP FIXME non-hail inline cheat 1 byte PIO read + */ + *data = get_DATA_B(); } } else { - m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t)); - eh = mtod(m, struct ether_header *); - data = mtod(m, u_int8_t *); - if (packetlen > 3) - bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, - (u_int32_t *)data, packetlen >> 2); - if (packetlen & 3) { - data += packetlen & ~3; - *((u_int32_t *)data) = - bus_space_read_stream_4(bst, bsh, DATA_REG_W); - } + panic("%s:%d: SMC_FLAGS_32BIT_READ", __FUNCTION__, __LINE__); } ifp->if_ipackets++; @@ -1289,16 +1336,16 @@ /* * Tell the card to free the memory occupied by this packet. */ - while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) - /* XXX bound this loop! */ ; - bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); + while (get_MMUCR_BUSY() != 0) + ; + set_MMUCR_CMD(MMUCR_RX_FIFO_RnR); /* * Check for another packet. */ - packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); - if (packetno & FIFO_REMPTY) + if (get_FIFO_REMPTY()) return; + goto again; } @@ -1468,21 +1515,18 @@ smc91cxx_stop(sc) struct smc91cxx_softc *sc; { - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; - /* * Clear interrupt mask; disable all interrupts. */ SMC_SELECT_BANK(sc, 2); - bus_space_write_2(bst, bsh, INTR_STAT_REG_W, 0); + set_MSK(0); /* * Disable transmitter and receiver. */ SMC_SELECT_BANK(sc, 0); - bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); - bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); + set_RCR(0); + set_TCR(0); /* * Cancel watchdog timer. @@ -1497,7 +1541,6 @@ smc91cxx_enable(sc) struct smc91cxx_softc *sc; { - if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { if ((*sc->sc_enable)(sc) != 0) { printf("%s: device enable failed\n", @@ -1517,7 +1560,6 @@ smc91cxx_disable(sc) struct smc91cxx_softc *sc; { - if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { (*sc->sc_disable)(sc); sc->sc_flags &= ~SMC_FLAGS_ENABLED; @@ -1580,10 +1622,7 @@ smc91cxx_mii_bitbang_read(self) struct device *self; { - struct smc91cxx_softc *sc = (void *) self; - - /* We're already in bank 3. */ - return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); + return (u_int32_t)get_MGMT(); } void @@ -1591,10 +1630,7 @@ struct device *self; u_int32_t val; { - struct smc91cxx_softc *sc = (void *) self; - - /* We're already in bank 3. */ - bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); + set_MGMT((u_int16_t)val); } int @@ -1602,7 +1638,6 @@ struct device *self; int phy, reg; { - struct smc91cxx_softc *sc = (void *) self; int val; SMC_SELECT_BANK(sc, 3); @@ -1619,8 +1654,6 @@ struct device *self; int phy, reg, val; { - struct smc91cxx_softc *sc = (void *) self; - SMC_SELECT_BANK(sc, 3); mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); @@ -1633,17 +1666,12 @@ struct device *self; { struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; - bus_space_tag_t bst = sc->sc_bst; - bus_space_handle_t bsh = sc->sc_bsh; - int mctl; SMC_SELECT_BANK(sc, 0); - mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); if (sc->sc_mii.mii_media_active & IFM_FDX) - mctl |= TCR_SWFDUP; + set_TCR_SWFDUP(1); else - mctl &= ~TCR_SWFDUP; - bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); + set_TCR_SWFDUP(0); SMC_SELECT_BANK(sc, 2); /* back to operating window */ } diff -Nru src/sys/dev/mii/sqphy.c.orig src/sys/dev/mii/sqphy.c --- src/sys/dev/mii/sqphy.c.orig 2005-09-13 14:55:37.000000000 -0700 +++ src/sys/dev/mii/sqphy.c 2005-09-13 14:56:41.000000000 -0700 @@ -88,7 +88,10 @@ #include #include -#include +static u_int16_t smc91c111_mii_get_2(unsigned long); +static void smc91c111_mii_set_2(unsigned long, u_int16_t); +extern char *smc91_base; +# include static int sqphymatch(struct device *, struct cfdata *, void *); static void sqphyattach(struct device *, struct device *, void *); @@ -122,6 +125,19 @@ NULL }, }; +struct mii_softc *sqphy_sc; +static u_int16_t +smc91c111_mii_get_2(unsigned long addr) +{ + return PHY_READ(sqphy_sc, addr); +} + +static void +smc91c111_mii_set_2(unsigned long addr, u_int16_t val) +{ + PHY_WRITE(sqphy_sc, addr, val); +} + static int sqphymatch(struct device *parent, struct cfdata *match, void *aux) { @@ -141,6 +157,7 @@ struct mii_data *mii = ma->mii_data; const struct mii_phydesc *mpd; + sqphy_sc = sc; mpd = mii_phy_match(ma, sqphys); aprint_naive(": Media interface\n"); aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); @@ -165,7 +182,7 @@ PHY_RESET(sc); sc->mii_capabilities = - PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + get_Status() & ma->mii_capmask; aprint_normal("%s: ", sc->mii_dev.dv_xname); if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0) aprint_error("no media present"); @@ -178,7 +195,6 @@ sqphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - int reg; if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0) return (ENXIO); @@ -198,8 +214,7 @@ * isolate ourselves. */ if (IFM_INST(ife->ifm_media) != sc->mii_inst) { - reg = PHY_READ(sc, MII_BMCR); - PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); + set_Control_MII_DIS(1); return (0); } @@ -241,28 +256,28 @@ { struct mii_data *mii = sc->mii_pdata; struct ifmedia_entry *ife = mii->mii_media.ifm_cur; - int bmsr, bmcr, status; + u_int16_t bmsr, bmcr, status; mii->mii_media_status = IFM_AVALID; mii->mii_media_active = IFM_ETHER; - bmsr = PHY_READ(sc, MII_BMSR) | - PHY_READ(sc, MII_BMSR); - if (bmsr & BMSR_LINK) + bmsr = get_Status(); + bmsr |= get_Status(); + if (mem_get_Status_LINK(bmsr)) mii->mii_media_status |= IFM_ACTIVE; - bmcr = PHY_READ(sc, MII_BMCR); - if (bmcr & BMCR_ISO) { + bmcr = get_Control(); + if (mem_get_Control_MII_DIS(bmcr)) { mii->mii_media_active |= IFM_NONE; mii->mii_media_status = 0; return; } - if (bmcr & BMCR_LOOP) + if (bmcr & HAIL_Control_LPBK_VAL(1)) mii->mii_media_active |= IFM_LOOP; - if (bmcr & BMCR_AUTOEN) { - if ((bmsr & BMSR_ACOMP) == 0) { + if (mem_get_Control_ANEG_EN(bmcr)) { + if (mem_get_Status_ANEG_ACK(bmsr) == 0) { /* Erg, still trying, I guess... */ mii->mii_media_active |= IFM_NONE; return; @@ -272,12 +287,12 @@ * supports the SPD_DET and DPLX_DET bits in * the STATUS register. */ - status = PHY_READ(sc, MII_SQPHY_STATUS); - if (status & STATUS_SPD_DET) + status = get_Status_Output(); + if (mem_get_Status_Output_SPDDET(status)) mii->mii_media_active |= IFM_100_TX; else mii->mii_media_active |= IFM_10_T; - if (status & STATUS_DPLX_DET) + if (mem_get_Status_Output_DPLXDET(status)) mii->mii_media_active |= IFM_FDX; } else mii->mii_media_active = ife->ifm_media; @@ -302,10 +317,9 @@ * This sucks. */ while ((sc->mii_inst == 0 || (sc->mii_flags & MIIF_NOISOLATE)) && - ((reg = PHY_READ(sc, MII_BMCR)) & BMCR_ISO) != 0) { - + ((reg = get_Control()) & HAIL_Control_MII_DIS_VAL(1)) != 0) { delay(35000); - PHY_WRITE(sc, MII_BMCR, reg & ~BMCR_ISO); + set_Control(reg & ~HAIL_Control_MII_DIS_VAL(1)); delay(35000); } }